module ClockDivider(
    input clk_100MHz,
    input rst_n,
    output reg clk_1Hz,
    output reg clk_10Hz,
    output reg clk_1kHz
);

    reg [26:0] cnt_1Hz;
    reg [23:0] cnt_10Hz;
    reg [16:0] cnt_1kHz;

    always @(posedge clk_100MHz or negedge rst_n) begin
        if(~rst_n) begin
            cnt_1Hz <= 0;
            clk_1Hz <= 0;
        end else if(cnt_1Hz == 49999999) begin
            cnt_1Hz <= 0;
            clk_1Hz <= ~clk_1Hz;
        end else cnt_1Hz <= cnt_1Hz + 1;
    end

    always @(posedge clk_100MHz or negedge rst_n) begin
        if(~rst_n) begin
            cnt_10Hz <= 0;
            clk_10Hz <= 0;
        end else if(cnt_10Hz == 4999999) begin
            cnt_10Hz <= 0;
            clk_10Hz <= ~clk_10Hz;
        end else cnt_10Hz <= cnt_10Hz + 1;
    end

    always @(posedge clk_100MHz or negedge rst_n) begin
        if(~rst_n) begin
            cnt_1kHz <= 0;
            clk_1kHz <= 0;
        end else if(cnt_1kHz == 49999) begin
            cnt_1kHz <= 0;
            clk_1kHz <= ~clk_1kHz;
        end else cnt_1kHz <= cnt_1kHz + 1;
    end
endmodule
